commercial temperature range idtcv141 1-to-8 differential clock buffer 1 october 2005 idtcv141 commercial temperature range 1-to-8 differential clock buffer the idt logo is a registered trademark of integrated device technology, inc. ? 2005 integrated device technology, inc. dsc 6738/19 features: ? compliant with intel db800 spec ? eight differential clock pairs at 0.7v ? 50ps skew ? 50ps cycle-to-cycle jitter ? programmable bandwidth ? pll bypass configurable ? divide by 2 programmable ? available in ssop and tssop packages functional block diagram description: the cv141 differential buffer is compliant with intel db800 specifications. it is intended to distribute the src (serial reference clock) as a companion chip to the main clock of the ck409, ck410/ck410m, ck410b, etc. pll is off in bypass mode and has no clock detect. div pll output buffer dif_0 dif_0# dif_1 dif_1# dif_2 dif_2# dif_3 dif_3# dif_4 dif_4# dif_5 dif_5# dif_6 dif_6# dif_7 dif_7# scl sda src_div2# src_in# src_in output control high_bw# pll/bypass# oe[7:0] src_stop p wrdwn sm bus controller lock oe_inv (1) (1) (1) note: 1. see oe_inv table for active high or active low.
commercial temperature range 2 idtcv141 1-to-8 differential clock buffer pin configuration symbol description min max unit v dda 3.3v core supply voltage 4.6 v v ddin 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ssop/ tssop top view 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 lock v dda v ssa iref oe_7 oe_4 dif_7 dif_7# oe_inv v dd dif_6 dif_6# oe_6 oe_5 dif_5 dif_5# v ss v dd dif_4 dif_4# high_bw# src_stop p wrdwn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 src_div2# v dd v ss src_in src_in# oe_0 oe_3 dif_0 dif_0# v ss v dd dif_1 dif_1# oe_1 oe_2 dif_2# v ss v dd dif_3 dif_3# pll/bpass# dif_2 scl sda v ss (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) oe functionality [oe_inv = 0] oe_[7:0] - pin oe_[7:0] - smbus bit dif_[7:0] diff_[7:0]# 1 1 normal normal 1 0 tristate tristate 0 1 tristate tristate 0 0 tristate tristate high_bw# selection high_bw# = 0 high_bw#=1 min. typ. max. min. typ. max. unit pll bw 2 3 4 0.7 1 1.4 mhz pll peaking ? 13 ? 13db oe_inv oe_inv = 0 oe_inv = 1 oe_[7:0] active high active low p wrdwn active low active high src_stop active low active high oe functionality [oe_inv = 1] oe_[7:0] - pin oe_[7:0] - smbus bit dif_[7:0] diff_[7:0]# 1 1 tristate tristate 1 0 tristate tristate 0 1 normal normal 0 0 tristate tristate note: 1. see oe_inv table for active high or active low.
commercial temperature range idtcv141 1-to-8 differential clock buffer 3 pin description pin name type pin # description src_in, src_in# in, dif 4,5 0.7v differential src input 8, 9, 12, 13, 16, 17, dif_[7:0], dif_ [7:0]# out, dif 20, 21, 29, 30, 33, 0.7v differential clock output 34, 37, 38, 41, 42 oe[7:0] in 6, 7, 14, 15, 3.3v lvttl input for enabling differential outputs (see oe_inv table) 35, 36, 43, 44 p wrdwn i n 26 3.3v lvttl for power down (see oe_inv table) iref in 46 reference current for differential output lock out 45 high, locked pll/bypass# in 22 1 = pll mode, 0 = bypass, pll off high_bw# in 28 0 = high bw, 1 = low bw (see high_bw# selection table) src_div2# in 1 low = divide by 2 mode src_stop in 27 src stop (see oe_inv table) scl i n 23 smbus clock sda i/o, open collector 24 smbus data oe_inv in 40 (see oe_inv table) index block write protocol bit # of bits from description 1 1 master start 2-9 8 master dch 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master dch 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master ddh 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes), power on is 8 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit.
commercial temperature range 4 idtcv141 1-to-8 differential clock buffer byte 0 bit output(s) affected description/function 0 1 type power on 7 powerdown dirve mode driven tri-state rw 0 6 src_stop# drive mode driven tri-state rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 high_bw# logically and with hw pin high band width low band width rw 1 1 pll/bypass# logically and with hw pin bypass pll mode rw 1 0 src_div2# logically and with hw pin divided by 2 normal rw 1 byte 2 bit output(s) affected description/function 0 1 type power on 7 diff_7 free running with src_stop# free stopped rw 0 6 diff_6 free running with src_stop# free stopped rw 0 5 diff_5 free running with src_stop# free stopped rw 0 4 diff_4 free running with src_stop# free stopped rw 0 3 diff_3 free running with src_stop# free stopped rw 0 2 diff_2 free running with src_stop# free stopped rw 0 1 diff_1 free running with src_stop# free stopped rw 0 0 diff_0 free running with src_stop# free stopped rw 0 byte 1 bit output(s) affected description/function 0 1 type power on 7 diff_7 output enable tristate enable rw 1 6 diff_6 output enable tristate enable rw 1 5 diff_5 output enable tristate enable rw 1 4 diff_4 output enable tristate enable rw 1 3 diff_3 output enable tristate enable rw 1 2 diff_2 output enable tristate enable rw 1 1 diff_1 output enable tristate enable rw 1 0 diff_0 output enable tristate enable rw 1 byte 3 bit output(s) affected description / function 0 1 type power on 7 reserved rw 6 reserved rw 5 reserved rw 4 reserved rw 3 reserved rw 2 reserved rw 1 reserved rw 0 reserved rw control registers
commercial temperature range idtcv141 1-to-8 differential clock buffer 5 byte 4 bit output(s) affected description / function 0 1 type power on 7 revision id r 0 6 revision id r 0 5 revision id r 0 4 revision id r 0 3 vendor id r 0 2 vendor id r 1 1 vendor id r 0 0 vendor id r 1 byte 62 = 10h byte 63 = 14h symbol parameter test conditions min. typ. max. unit v ih input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v i ih input high current v in = v dd ?5 ? 5 a i il1 input low current v in = 0v, inputs with no pull-up resistors ?5 ? ? a i il2 input low current v in = 0v, inputs with pull-up resistors ?200 ? ? a l pin pin inductance (2) ?? 7 nh c in input capacitance (2) logic inputs ? ? 5 pf c out output pin capacitance ? ? 6 electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%
commercial temperature range 6 idtcv141 1-to-8 differential clock buffer electrical characteristics - dif 0.7 current mode differential pair following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf symbol parameter (1) test conditions min. typ. max. unit v high voltage high +150 ? ? mv v low voltage low ? ? ?150 v max max input voltage measurement on single-ended signal using absolute value ? ? 1150 mv v min min input voltage ?300 ? ? v cross(abs) crossing voltage (abs) 250 ? 550 mv t r rise time v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation ? ? 125 ps d-t f fall time variation ? ? 125 ps d t3 duty cycle measurement from differential waveform 45 ? 55 % t sk 3 output pin-to-pin skew v t = 50% ? ? 50 ps t jcyc - cyc jitter, cycle to cycle (2) measurement from differential waveform ? ? 50 ps src_in 0.7v ac timing characteristics symbol parameter (1) min. max. unit rising edge rate rising edge rate 0.6 4 v/ns falling edge rate falling edge rate 0.6 4 v/ns v ih differential input high voltage +150 ? mv v il differential input low voltage ? ?150 mv v cross absolute crossing point voltages 250 550 mv v max absolute maximum input voltage ? + 1.15 v v min absolute minimum input voltage ?0.3 ? v duty cycle src_in duty cycle 45 55 % notes: 1. parameter is guaranteed by design, but not 100% production tested. 2. bypass mode, additive.
commercial temperature range idtcv141 1-to-8 differential clock buffer 7 dif ac timing characteristics pll bandwidth and peaking symbol parameter min typ max units t prop , pll src_in to dif propagation delay, pll mode (1) -250 ? 250 ps t prop , bypass src_in to dif propagation delay, bypass mode (1) 2.5 ? 4.5 ns t skew dif_[7:0] pin to pin skew (1) ? ? 250 ps pll bandwidth high_bw#=0 (high bandwidth) (1) 2 3 4 mhz pll bandwidth high_bw#=1 (low bandwidth) (1) 0.7 1 1.4 m h z pll peaking pll peaking (1,2) ?13db t ccjitter cycle to cycle jitter (1) ??50ps duty cycle pll mode (1) 45 ? 55 % duty cycle bypass (assume input is 50%) (1) 40 ? 60 % output control symbol parameter min typ max units t drive _p wr d wn clk driven from pd de_assertion ? ? 300 s t active _p wr d wn clk toggling from pd de_assertion ? ? 1 ms t active _oe clk toggling from oe_[7:0] assertion 2 ? 6 clock periods t inactive _oe clk tri-stated from oe_[7:0] de_assertion 2 ? 6 clock periods pwrdwn (oe_inv = 0) the p wrdwn signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of dif# to be recognized as a valid assertion or de-assertion. p wrdwn dif dif# 1 normal normal 0 iref*2 or float float src_stop (oe_inv = 0) the src_stop signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of dif# to be recognized as a valid assertion or de- assertion. src_stop dif dif# 1 normal normal 0 iref*6 or float float pwrdwn (oe_inv = 1) p wrdwn dif dif# 1 iref*2 or float float 0 normal normal src_stop (oe_inv = 1) src_stop dif dif# 1 iref*6 or float float 0 normal normal notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. measured at 3db downpoint.
commercial temperature range 8 idtcv141 1-to-8 differential clock buffer src_stop = driven, pwrdwn = driven dif (free running) src_stop p wrdwn (1) (1) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop = tristate, pwrdwn = driven dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop p wrdwn (1) (1) src stop functionality the src_stop signal is an input controlling dif[7:0] and dif[7:0] # outputs. this signal can be asserted asynchronously. src_ stop is active high when oe_inv = high (see oe_inv table). note: 1. the polarity depends on oe_inv.
commercial temperature range idtcv141 1-to-8 differential clock buffer 9 src_stop = driven, pwrdwn = tristate dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop p wrdwn (1) (1) src_stop = tristate, pwrdwn = tristate dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop p wrdwn (1) (1) note: 1. the polarity depends on oe_inv.
commercial temperature range 10 idtcv141 1-to-8 differential clock buffer ordering information xxx xx package pv pvg pa pag small shrink outline package ssop - green thin small shrink outline package tssop - green 1-to-8 differential clock buffer 141 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
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